The initial part was , a later A suffix version was upward compatible and usable with the or processor. The combines multiple interrupt input sources into a single interrupt output to the host microprocessor, extending the interrupt levels available in a system beyond the one or two levels found on the processor chip. The was introduced as part of Intel's MCS 85 family in However, while not anymore a separate chip, the A interface is still provided by the Platform Controller Hub or Southbridge chipset on modern x86 motherboards. Up to eight slave s may be cascaded to a master to provide up to 64 IRQs.
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July Description Figure 1. Marking high. Port ". Built-in two A compatible interrupt controllers. Abstract: lt6ma 02F9 oti chipset NEC serial port intel sx Text: control logic indudes two Intel A compatible interrupt controllers. Blue Chip Technology Ltd. Built-in two compatible DMA controllers. Abstract: M M Text: information. Controller which is a superset of the A ; four 16bit Programmable Interval Timers which are , equivalent of three enhanced A Programmable Interrupt Controllers.
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PROGRAMMABLE INTERRUPT CONTROLLER
OVP Peripheral Model: Intel8259A
8259A CONTROLLER. Datasheet pdf. Equivalent